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zeST, new FPGA project (10.09.2021 - 23:05 Uhr)

Not all FPGAs are the same and an existing core must first be ported to another FPGA family. With the zeST project, the Xilinx Zync-7000 family now has the pleasure of an ST/E replica. The CPU replication is based on the free fx68k implementation of the 68000. zeST still lacks a comfortable user interface; it is booted via a setup program using Linux.

Developer Fran├žois Galea uses the project to learn VHDL. He wants to inform about progress on Twitter.

The Zync-7000 family combines an FPGA chip with a dual-core 32-bit ARM CPU and various hardware controllers.

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